
Si5040
TxdLosAssertThresh[7:0] (Bit 7:0, Register 145)
TxdLosClearThresh (Bit 7:0, Register 146)
dLosEn[1:0]
EN
DLOS
Monitor
dLOS
(Bit 2, Register 139)
LOS
(Bit 5, Register 137 or
Bit 0, Register 139)
(Bit 2:1, Register 138)
00: Disabled (Default)
01: Based on consecutive number of 1s
01: Based on consecutive number of 0s
01: Based on either consecutive number of 1s or 0s
TxSqmThresh[5:0] (Bit 7:2, Register 154)
TxSqmDeassertThresh[5:0] (Bit 5:0, Register 155)
1
EN
Signal
Quality
Monitor
sqmAlarm
(Bit 0, Register 137)
sqmLOS
(Bit 4, Register 139)
sqmLosEn
(Bit 3, Register 138, Default= 0)
TxSqmValue[5:0]
(Bit 5:0, Register 153)
SqmLol
1 (Default)
Tx Recovered Clock
Reference Clock
Frequency
Offset
Monitor
FreqLol
0
Select
LOL
(Bit 4, Register 137)
lolMode
useLolMod
(Bit 2, Register 135) (Bit 3, Register 135, Default= 0)
Figure 16. TX LOS and LOL Block Diagram
Rev. 1.3
27